Ph.D. Thesis
Awards
Publications
Co-authored
Publications
Related Ph.D.
Theses
Study Theses
Ph.D. Study
Ph.D. Thesis
[Toc]
[Top]published in
Series in Microelectronics at Hartung-Gorre
printing house, Konstanz, Germany |
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Peter Jan Luethi, VLSI Circuits for MIMO Preprocessing, Hartung-Gorre, 2010, Ph.D. dissertation, ETH Zurich, Zurich, Switzerland Excerpt with ToC, Ordering Information |
Awards
[Toc] [Top]
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| May 2009 |
1st Place Winner of ISCAS'09 Live
Demonstration Contest, IEEE International Symposium on
Circuits and Systems (ISCAS), May 2009, Taipei,
Taiwan |
| Sept. 2008 |
2nd Place Winner of WinTech'08
Live Demonstration Contest, ACM International
Conference on Mobile Computing and Networking (MobiCom),
Sept. 2008, San Francisco, CA, USA |
| May 2008 |
ISCAS 2008 Student Best Paper Award,
Co-Author, IEEE International Symposium of Circuits and
Systems (ISCAS), May 2008, Seattle, WA, USA |
| March 2003 |
Best
Presentation Award, 3rd annual European Specman User
Group Conference, Design, Automation, and Test in Europe
(DATE) Conference, March 2003, Munich, Germany |
| May 2001 |
First
AMD Fab30 General-Manager Award, Dresden Design Center,
Advanced Micro Devices (AMD) Inc., Dresden,
Germany |
| July 1999 |
3rd Place Winner Swiss SmartROB
Championships, ETH Zurich, Zurich, Switzerland |
Publications [Toc] [Top]
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| P. Luethi, M. Wenk, T. Koch, M. Lerjen, N.
Felber, W. Fichtner, Multi-user MIMO Testbed, in Proc. of ACM MobiCom'08 / WiNTECH'08 Workshop with Live Demonstration Contest, San Francisco, CA, USA, Sept. 2008, pp. 109-110 |
| P. Luethi, C. Studer, S. Duetsch, E.
Zgraggen, H. Kaeslin, N. Felber, W. Fichtner, Gram-Schmidt-based QR Decomposition for MIMO Detection: VLSI Implementation and Comparison, in Proc. of IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Macao, China, Nov. 2008, pp. 830-833 |
| P. Luethi, A. Burg, S. Haene, D. Perels,
N. Felber, W. Fichtner, VLSI Implementation of a High-Speed Iterative Sorted MMSE QR Decomposition, in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), New Orleans, LA, USA, May 2007, pp. 1421-1424 |
| P. Luethi, U. Hensel, Verification Glue: How to compose System-Level Environments, 3rd Annual European Specman User Group Conference, DATE03, Munich, Germany, Mar. 2003 |
| P. Luethi, T. Roewer, M. Stadler, D.
Forrer, S. Moscibroda, N. Felber, H. Kaeslin, W.
Fichtner, A Parametrizable Hybrid Stack-Register Processor as Soft Intellectual Property Module, in Proc. of IEEE International ASIC/SOC Conference (ASIC-SOC), Washington DC, USA, Sept. 2000, pp. 87-91 |
Co-authored
Publications [Toc] [Top]
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| M. Wenk, P. Luethi, T. Koch, P. Maechler,
M. Lerjen, N. Felber, W. Fichtner, Hardware Platform and Implementation of a Real-Time Multi-User MIMO-OFDM Testbed, in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), Taipei, Taiwan, May 2009, pp. 789-792 |
| C. Studer, P. Luethi, W. Fichtner, VLSI Architecture for Data-Reduced Steering Matrix Feedback in MIMO Systems, in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), Seattle, Washington, USA, May 2008, pp. 300-303 |
| C. Senning, C. Studer, P. Luethi, W.
Fichtner, Hardware-Efficient Steering Matrix Computation Architecture for MIMO Communication Systems, in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), Seattle, Washington, USA, May 2008, pp. 304-307 |
| S. Heinzle, O. Saurer, S. Axmann, D.
Browarnik, A. Schmidt, F. Carbognani, P. Luethi, N. Felber,
M. Gross, A Transform, Lighting and Setup ASIC for Surface Splatting, in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), Seattle, WA, USA, May 2008, pp. 2813-2816 |
| S. Haene, A. Burg, P. Luethi, N. Felber,
W. Fichtner, FFT Processor for OFDM Channel Estimation, in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), New Orleans, LA, USA, May 2007, pp. 1417-1420 |
| C. Hess, M. Wenk, A. Burg, P. Luethi, C.
Studer, N. Felber, W. Fichtner, Reduced-complexity MIMO Detector with close-to ML Error Rate Performance, in Proc. of ACM Great Lakes Symposium on VLSI (GLSVLSI), Mar. 2007, pp. 200-203 |
| A. Burg, S. Haene, D. Perels, P. Luethi,
N. Felber, W. Fichtner, Algorithm and VLSI Architecture for Linear MMSE Detection in MIMO-OFDM Systems, in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), May 2006, pp. 4102-4105 |
| D. Perels, S. Haene, A. Burg, P. Luethi,
N. Felber, W. Fichtner, A Frame-Start Detector for a 4x4 MIMO-OFDM System, in Proc. of IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), May 2006, vol. 4, pp. 425-428 |
| S. Haene, A. Burg, D. Perels, P. Luethi,
N. Felber, W. Fichtner, FPGA Implementation of Viterbi Decoders for MIMO-BICM, in Proc. of 39th Asilomar Conference on Signals, Systems, and Computers, Monterey, CA, USA, Oct. 2005 |
| S. Haene, A. Burg, D. Perels, P. Luethi,
N. Felber, W. Fichtner, Silicon Implementation of an MMSE-based Soft Demapper for MIMO-BICM, in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), May 2006, pp. 2597-2600 |
| F.K. Guerkaynak, P. Luethi, N. Bernold, R.
Blattmann, V. Goode, M. Marghitola, H. Kaeslin, N. Felber,
W. Fichtner, Hardware Evaluation of eSTREAM Candidates: Achterbahn, Grain, MICKEY, MOSQUITO, SFINKS, Trivium, VEST, ZK-Crypt, in Proc. of The State of the Art of Stream Ciphers (SASC) - Special Workshop hosted by the ECRYPT Network of Excellence, Leuven, Belgium, Feb. 2006 |
| D. Perels, S. Haene, P. Luethi, A. Burg,
N. Felber, W. Fichtner, H. Boelcskei, ASIC Implementation of a MIMO-OFDM Transceiver for 192 Mbps WLANs, in Proc. of IEEE European Solid-State Circuits Conference (ESSCIRC), Grenoble, France, Sept. 2005, pp. 215-218 |
| A. Burg, S. Haene, D. Perels, P. Luethi,
N. Felber, W. Fichtner, Receiver Design for Multi-Antenna Wireless Communications, in Proc. of IEEE Conference on Research in Microelectronics (PRIME 2005), Lausanne, Switzerland, July 2005, vol. 2, pp. 35-38 |
Related Ph.D. Theses
[Toc]
[Top]all published in
Series in Microelectronics at Hartung-Gorre
printing house, Konstanz, Germany |
| Andreas Burg, VLSI Circuits for MIMO Communication Systems, Hartung-Gorre, 2006, Ph.D. dissertation, ETH Zurich, Zurich, Switzerland |
| Simon Haene, VLSI Circuits for MIMO-OFDM Physical Layer, Hartung-Gorre, 2008, Ph.D. dissertation, ETH Zurich, Zurich, Switzerland |
| Christoph David Perels, Frame-Based MIMO-OFDM Systems: Impairment Estimation and Compensation, Hartung-Gorre, 2008, Ph.D. dissertation, ETH Zurich, Zurich, Switzerland |
| Christoph Studer, Iterative MIMO Decoding: Algorithms and VLSI Implementation Aspects, Hartung-Gorre, 2009, Ph.D. dissertation, ETH Zurich, Zurich, Switzerland |
| Stefan Eberli, Application-Specific Processor for MIMO-OFDM Software-Defined Radio, Hartung-Gorre, 2009, Ph.D. dissertation, ETH Zurich, Zurich, Switzerland |
| Markus Wenk, MIMO-OFDM Testbed: Challenges, Implementations, and Measurement Results, Hartung-Gorre, 2010, Ph.D. dissertation, ETH Zurich, Zurich, Switzerland |
Study Theses [Toc] [Top] |
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| Swiss SmartROB Championships | |
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Autonomously navigating and
mail-collecting robot The robot contest I've participated in during the summer semester 1999 at the Swiss Federal Institute of Technology, Zurich, Switzerland. Project duration: April 1999 - July 1999 |
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The task was to develop an autonomously navigating robot,
which had to be able to detect and collect letters - also
autonomously. The letters were distributed in a square
area of 7.9 x 7.9 meters, which was designed as a
labyrinth.
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| Enhanced RISC Processor "SILVERBIRD" | |
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Parametrizable Hybrid
Stack-Register Processor as VHDL Soft IP-Module Students project at the Integrated Systems Laboratory of the Swiss Federal Institute of Technology, Zurich, Switzerland. Project duration: October 1999 - July 2000 |
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The aim was to develop a highly parametrizable RISC processor as soft IP (Intellectual Property) module based on VHDL (Very high speed integrated circuits Hardware Description Language) for embedded systems. Features:
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| Low-Cost Inertial Navigation System | |
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Design and characterization of a
strapdown inertial navigation system based on low-cost
sensors Students project I've participated in during the summer semester 2000 at the Swiss Federal Institute of Technology, Zurich, Switzerland. Project duration: April 2000 - July 2000 |
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The aim of the project was to design a complete inertial
navigation system (INS) based on cost-effective
solid-state sensors and to assess and characterize the
platform's precision and performance. Finally, we had to
provide feedback about possible improvements and
performance enhancements. In 2008/2009, this thesis
served as 'work of prior art' in a patent
infringement case settled at the International Trade
Commission in the United States.
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| Performance Analysis of next-generation AMD Southbridge "Zorak" | |
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Implementation of a
performance test environment capable of revealing possible
performance bottlenecks already during design
time My master's thesis at AMD Dresden Design Center, Dresden, Germany in order to get my master degree in electrical engineering from the Swiss Federal Institute of Technology, Zurich, Switzerland. Project duration: October 2000 - March 2001 |
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In 2000, the "Zorak" Southbridge was a prototype device for the chipset of the AMD 64-bit "hammer series" processors – the powerful "Sledgehammer" processor and his smaller counterpart, the "Clawhammer" processor. My task was to setup a performance analysis environment for the "Zorak" Southbridge being capable of revealing possible performance bottlenecks already during RTL design time and providing corresponding suggestions for performance enhancements. The performance analysis should cover the entire Southbridge with all its specific bus protocols, and at that time, also the new Lightning Data Transport (LDT) bus, now officially known as HyperTransport™ (HT). The LDT bus, developed and standardized by a special interest group including AMD, was implemented between North- and Southbridge and served for instance the 64-bit/66 MHz PCI bus bridges and the peripheral devices attached to the Southbridge. < This project is confidential, therefore no more information available. > After completing this master's thesis in early 2001, I started working at the AMD Dresden Design Center, in Dresden, Germany, focusing on RTL-based block- and system-level verification and performance analysis. I was involved with functional verification and interoperability tests of several HyperTransport™ Southbridges for AMD's K8 CPUs. |
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Ph.D. Study
[Toc]
[Top]
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| VLSI Circuits for MIMO Preprocessing | |
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Research activities
in the field of fourth-generation MIMO wireless
communication My work focuses on VLSI circuits for MIMO preprocessing, with emphasis on QR decomposition-based architectures, and contains considerations for joint algorithmic and architectural optimizations. Several architectures have been realized as integrated circuits, including one proving its full operational capabilities by being successfully deployed to a real-time 4x4 MIMO-OFDM testbed with embedded MAC layer processing. |
Last updated: 2010/09/16
