| 3 March, 2003 | |
| Registration and breakfast | 8:30 - 9:00 a.m. |
|
Welcome Sean Redmond, Verisity Design |
9:00 - 9:15 a.m. |
|
Keynote Yoav Hollander |
9:15 - 9:45 a.m. |
|
Platform Validation Methodology Andrew Nightingale, ARM |
9:45 - 10:30 a.m. |
|
ATA/ATAPI-4 Device Controller Verification Giovanni Auditore, STMicroelectronics |
10:30 - 11:15 a.m. |
| Break | 11:15 - 11:30 a.m. |
|
Reusability and Modularity in SoC Verification Darren Galpin, Infineon |
11:30 - 12:10 p.m. |
|
Multiple Interface Cross-Checking in a Single eVC
Architecture Aggelos loannou, Thanasis Oikonomou, Stelios Diamantidis, Globetech Solutions |
12:10 - 12:45 p.m. |
| Lunch | 12:45 - 2:00 p.m. |
|
ImPROVE-HDL: Formal Property Checking within Specman Elite Imed Moussa, TNI-Valiosys |
2:00 - 2:45 p.m. |
|
Lessons Learnt: System-Verification Methodology and Specman
Elite Andreas Dieckmann, Siemens |
2:45 - 3:30 p.m. |
| Break | 3:30 - 3:45 p.m. |
|
Hardware Verification with e and Unified
Modeling Language Ingo Kühn, AMD |
3:45 - 4:30 p.m. |
|
Verification Glue: How to Compose System Level Environments
Peter Lüthi, AMD |
4:30 - 5:15 p.m. |
|
A Novel flow for Error Injection and checking in SoC Verification Achutha Jois, Sasken Communication Technologies Limited |
5:15 - 5:50 p.m. |
|
Closing Remarks Sean Redmond, Verisity Design |
5:50 p.m. |
| Cocktail reception | 5:50 - 7:00 p.m. |